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FEATURES 65 MSPS Guaranteed Sample Rate 40 MSPS Version Available Sampling Jitter < 300 fs 100 dB Multitone SFDR 1.3 W Power Dissipation Differential Analog Inputs Digital Outputs Two's Complement Format 3.3 V CMOS-Compatible Data Ready for Output Latching APPLICATIONS Multichannel, Multimode Receivers AMPS, IS-136, CDMA, GSM, Third Generation Single Channel Digital Receivers Antenna Array Processing Communications Instrumentation Radar, Infrared Imaging Instrumentation
14-Bit, 40 MSPS/65 MSPS A/D Converter AD6644
Designed for multichannel, multimode receivers, the AD6644 is part of ADI's new SoftCellTM transceiver chipset. The AD6644 achieves 100 dB multitone, spurious-free dynamic range (SFDR) through the Nyquist band. This breakthrough performance eases the burden placed on multimode digital receivers (software radios) which are typically limited by the ADC. Noise performance is exceptional; typical signal-to-noise ratio is 74 dB. The AD6644 is also useful in single channel digital receivers designed for use in wide-channel bandwidth systems (CDMA, W-CDMA). With oversampling, harmonics can be placed outside the analysis bandwidth. Oversampling also facilitates the use of decimation receivers (such as the AD6620), allowing the noise floor in the analysis bandwidth to be reduced. By replacing traditional analog filters with predictable digital components, modern receivers can be built using fewer "RF" components, resulting in decreased manufacturing costs, higher manufacturing yields, and improved reliability. The AD6644 is built on Analog Devices' high-speed complementary bipolar process (XFCB) and uses an innovative, multipass circuit architecture. Units are packaged in a 52-terminal LowProfile Quad Plastic Flatpack (LQFP) specified from -25C to +85C.
PRODUCT HIGHLIGHTS
PRODUCT DESCRIPTION
The AD6644 is a high-speed, high-performance, monolithic 14-bit analog-to-digital converter. All necessary functions, including track-and-hold (T/H) and reference, are included onchip to provide a complete conversion solution. The AD6644 provides CMOS-compatible digital outputs. It is the third generation in a wideband ADC family, preceded by the AD9042 (12-bit 41 MSPS) and the AD6640 (12-bit 65 MSPS, IF sampling.)
1. Guaranteed sample rate is 65 MSPS. 2. Fully differential analog input stage. 3. Digital outputs may be run on 3.3 V supply for easy interface to digital ASICs. 4. Complete Solution: reference and track-and-hold. 5. Packaged in small, surface-mount, plastic, 52-terminal LQFP.
FUNCTIONAL BLOCK DIAGRAM
AVCC DVCC
AIN A1 AIN TH1 TH2 A2 TH3 TH4 TH5 ADC3
VREF
2.4V
ADC1 5
DAC1
ADC2 5
DAC2
6
AD6644
ENCODE ENCODE
INTERNAL TIMING MSB GND DMID OVR DRY D13 D12
DIGITAL ERROR CORRECTION LOGIC LSB D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SoftCell is a trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD6644-SPECIFICATIONS
DC SPECIFICATIONS (AV
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error POWER SUPPLY REJECTION (PSRR) REFERENCE OUT (VREF) ANALOG INPUTS (AIN, AIN) Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance POWER SUPPLY Supply Voltage AVCC1 DVCC Supply Current IAVCC (AVCC = 5.0 V) IDVCC (DVCC = 3.3 V) POWER CONSUMPTION Full Full Full Full Full Full Full Full Full Full Full 25C II II II II V V V V V V V V
CC
= 5 V, DVCC = 3.3 V; TMIN = -25 C, TMAX = +85 C)
Temp Test Level Min AD6644AST-40 Typ Max 14 Guaranteed 3 -6 0.25 0.50 10 95 1.0 2.4 2.2 1 1.5 Min AD6644AST-65 Typ Max 14 Guaranteed 3 -6 0.25 0.50 10 95 1.0 2.4 2.2 1 1.5 Unit Bits
-10 -10 -1.0
+10 +10 +1.5
-10 -10 -1.0
+10 +10 +1.5
mV % FS LSB LSB ppm/C ppm/C mV/V V V p-p k pF
Full Full Full Full Full
II II II II II
4.85 3.0
5.0 3.3 245 30 1.3
5.25 3.6 276 36 1.5
4.85 3.0
5.0 3.3 245 30 1.3
5.25 3.6 276 36 1.5
V V mA mA W
NOTES 1 AVCC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameter ENCODE INPUTS (ENC, ENC) Differential Input Voltage1 Differential Input Resistance Differential Input Capacitance LOGIC OUTPUTS (D13-D0, DRY, OVR) Logic Compatibility Logic "1" Voltage2 Logic "0" Voltage2 Output Coding DMID
(AVCC = 5 V, DVCC = 3.3 V; TMIN = -25 C, TMAX = +85 C)
Temp Full 25C 25C Test Level IV V V Min 0.4 10 2.5 CMOS 2.5 0.4 Two's Complement DVCC/2 AD6644AST-40 Typ Max Min 0.4 10 2.5 CMOS 2.5 0.4 Two's Complement DVCC/2 AD6644AST-65 Typ Max Unit V p-p k pF
Full Full Full
V V V
V V V
NOTES 1 All ac specifications tested by driving ENCODE and ENCODE differentially. Reference Figure 22 for performance versus encode power. 2 Digital output logic levels: DV CC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF will degrade performance. Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Parameter Maximum Conversion Rate Minimum Conversion Rate ENCODE Pulsewidth High ENCODE Pulsewidth Low
Specifications subject to change without notice.
(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; TMIN = -25 C, TMAX = +85 C)
Test Level II IV IV IV Min 40 15 10 10 6.5 6.5 AD6644AST-40 Typ Max Min 65 15 AD6644AST-65 Typ Max Unit MSPS MSPS ns ns
Temp Full Full Full Full
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AD6644 AC SPECIFICATIONS1 (AV
Parameter SNR Analog Input @ -1 dBFS SINAD2 Analog Input @ -1 dBFS 2.2 MHz 15.5 MHz 30.5 MHz 2.2 MHz 15.5 MHz 30.5 MHz
CC
= 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; TMIN = -25 C, TMAX = +85 C)
Temp 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C Full Test Level II II II II II V II II V II II V V V V Min AD6644AST-40 Typ Max 74.5 74.0 73.5 74.5 74.0 73.0 92 90 85 93 92 92 100 90 250 Min 72 72 72 72 72 AD6644AST-65 Typ Max 74.5 74.0 73.5 74.5 74.0 73.0 92 90 85 93 92 92 100 90 250 Unit dB dB dB dB dB dB dBc dBc dBc dBc dBc dBc dBFS dBc MHz
WORST HARMONIC (2ND or 3RD)2 Analog Input 2.2 MHz @ -1 dBFS 15.5 MHz 30.5 MHz WORST HARMONIC (4TH or Higher)2 Analog Input 2.2 MHz @ -1 dBFS 15.5 MHz 30.5 MHz TWO-TONE SFDR2, 3, 4 TWO-TONE IMD REJECTION F1, F2 @ -7 dBFS
2, 4
83 83
85 85
Full 25C
ANALOG INPUT BANDWIDTH
NOTES 1 All ac specifications tested by driving ENCODE and ENCODE differentially. 2 AVCC = 5 V to 5.25 V for rated ac performance. 3 Analog input signal power swept from -7 dBFS to -100 dBFS. 4 F1 = 15 MHz, F2 = 15.5 MHz. Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Parameter ENCODE INPUT PARAMETERS Encode Period1 @ 65 MSPS Encode Period1 @ 40 MSPS Encode Pulsewidth High2 @ 65 MSPS Encode Pulsewidth Low @ 65 MSPS ENCODE/DATA READY Encode Rising to Data Ready Falling Encode Rising to Data Ready Rising @ 65 MSPS (50% Duty Cycle) @ 40 MSPS (50% Duty Cycle) ENCODE/DATA (D13:0), OVR ENC to DATA Falling Low ENC to DATA Rising Low ENCODE to DATA Delay (Hold Time)3 ENCODE to DATA Delay (Setup Time)4 Encode = 65 MSPS (50% Duty Cycle) Encode = 40 MSPS (50% Duty Cycle)
1
(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; TMIN = -25 C, TMAX = +85 C, CLOAD = 10 pF)
Name tENC tENC tENCH tENCL tDR tE_DR Temp Full Full Full Full Full Full Full tE_FL tE_RL tH_E tS_E Full Full Full Full Full Test Level V V IV IV IV IV IV IV IV IV IV IV Min AD6644AST-40/65 Typ Max 15.4 25 7.7 7.7 3.4 tENCH + tDR 11.1 15.9 5.5 4.3 4.3 tENC - tE_FL 9.8 19.4 Unit ns ns ns ns ns ns ns ns ns ns ns ns
6.2 6.2 2.6 10.3 15.1 3.8 3.0 3.0 6.2 15.9
9.2 9.2 4.6 12.3 17.1 9.2 6.4 6.4 11.6 21.2
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AD6644-SPECIFICATIONS
Parameter DATA READY (DRY5)/DATA, OVR Data Ready to DATA Delay (Hold Time)2 Encode = 65 MSPS (50% Duty Cycle) Encode = 40 MSPS (50% Duty Cycle) Data Ready to DATA Delay (Setup Time)2 @ 65 MSPS (50% Duty Cycle) @ 40 MSPS (50% Duty Cycle) APERTURE DELAY APERTURE UNCERTAINTY (JITTER) Name tH_DR Full Full tS_DR Full Full tA tJ 25C 25C IV IV V V 3.2 8.0 IV IV 8.0 12.8 Temp Test Level Min AD6644AST-40/65 Typ Max Note 6 8.6 13.4 Note 6 5.5 10.3 100 0.2 Unit 9.4 14.2 6.5 11.3 ns ns ns ns ps ps rms
NOTES 1 Several timing parameters are a function of t ENC and tENCH. 2 To compensate for a change in duty cycle for t H_DR and tS_DR use the following equation: NewtH_DR = (tH_DR - % Change(tENCH)) x tENC/2 NewtS_DR = (tS_DR - % Change(tENCH)) x tENC/2. 3 ENCODE to DATA Delay (Hold Time) is the absolute minimum propagation delay through the analog-to-digital converter. 4 ENCODE to DATA Delay (Setup Time) is calculated relative to 65 MSPS (50% duty cycle). In order to calculate t S_E for a given encode use the following equation: NewtS_E = tENC(NEW) - tENC + tS_E (i.e., for 40 MSPS: NewtS_E(TYP) = 25 x 10-9 - 15.38 x 10-9 + 9.8 x 10-9 = 19.4 x 10 -9). 5 DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY. 6 Data Ready to DATA Delay(t H_DR and tS_DR) is calculated relative to 65 MSPS (50% duty cycle) and is dependent on t ENC and duty cycle. In order to calculate t H_DR and tS_DR for a given encode use the following equations: NewtH_DR = tENC(NEW)/2 - tENCH + tH_DR (i.e., for 40 MSPS: Newt H_DR(TYP) = 12.5 x 10-9 - 7.69 x 10-9 + 8.6 x 10-9 = 13.4 x 10-9 NewtS_DR = tENC(NEW)/2 - tENCH + tS_DR (i.e., for 40 MSPS: NewtS_DR(TYP) = 12.5 x 10-9 - 7.69 x 10-9 + 5.5 x 10-9 = 10.3 x 10-9. Specifications subject to change without notice.
tA
N3 N
AIN N1 N2
N4
t ENC
t ENCH
t ENCL
ENC, ENC
N
N1
N2
N3
N4
t E_FL t E_RL
D[13:0], OVR N-3 N-2
t E_DR
t S_E
N-1 N
t H_E
t DR
DRY
t S_DR
t H_DR
Figure 1. Timing Diagram
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AD6644
ABSOLUTE MAXIMUM RATINGS 1
Parameter ELECTRICAL AVCC Voltage DVCC Voltage Analog Input Voltage Analog Input Current Digital Input Voltage Digital Output Current
Min 0 0 0 0
Max 7 7 AVCC 25 AVCC 4
Unit V V V mA V mA
EXPLANATION OF TEST LEVELS Test Level
I II
100% production tested. 100% production tested at 25C, and guaranteed by design and characterization at temperature extremes. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only.
ENVIRONMENTAL2 Operating Temperature Range (Ambient) -25 Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) -65
+85 150 300 +150
C C C C
NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances (52-terminal LQFP); JA = 33C/W; JC = 11C/W. These measurements were taken on a 6 layer board in still air with a solid ground plane.
ORDERING GUIDE
Model AD6644AST-40 AD6644AST-65 AD6644ST/PCB
Temperature Range -25C to +85C (Ambient) -25C to +85C (Ambient)
Package Description 52-Terminal LQFP (Low-Profile Quad Plastic Flatpack) 52-Terminal LQFP (Low-Profile Quad Plastic Flatpack) Evaluation Board with AD6644AST-65
Package Option ST-52 ST-52
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6644 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD6644
PIN FUNCTION DESCRIPTIONS
Pin No. 1, 33, 43 2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, 29, 34, 42 3 5 6 8, 9, 14, 16, 18, 22, 26, 28, 30 11 12 20 24 31 32 35 36 37-41, 44-50 51 52
Name DVCC GND VREF ENCODE ENCODE AVCC AIN AIN C1 C2 DNC OVR DMID D0 (LSB) D1-D5, D6-D12 D13 (MSB) DRY
Function 3.3 V Power Supply (Digital) Output Stage Only. Ground. 2.4 V (Analog Reference). Bypass to ground with 0.1 F microwave chip capacitor. Encode Input; conversion initiated on rising edge. Complement of ENCODE; differential input. 5 V Analog Power Supply. Analog Input. Complement of AIN; Differential Analog Input. Internal Voltage Reference; bypass to ground with 0.1 F microwave chip capacitor. Internal Voltage Reference; bypass to ground with 0.1 F microwave chip capacitor. Do not connect this pin. Overrange Bit; high indicates analog input exceeds FS. Output Data Voltage Midpoint; approximately equal to (DVCC)/2. Digital Output Bit (Least Significant Bit); Two's Complement Digital Output Bits in Two's Complement. Digital Output Bit (Most Significant Bit); Two's Complement. Data Ready Output.
PIN CONFIGURATION
DRY D13 (MSB)
D6 DVCC
GND D5
D12 D11
D10 D9
D8 D7
52 51 50 49 48 47 46 45 44 43 42 41 40
D4
DVCC 1 GND 2 VREF 3 GND 4 ENCODE 5 ENCODE 6 GND 7 AVCC 8 AVCC 9 GND 10 AIN 11 AIN 12 GND 13
PIN 1 IDENTIFIER
39 38 37 36 35
D3 D2 D1 D0 (LSB) DMID GND DVCC OVR DNC AVCC GND AVCC GND
AD6644
TOP VIEW (Not to Scale)
34 33 32 31 30 29 28 27
14 15 16 17 18 19 20 21 22 23 24 25 26
AVCC
AVCC
DNC = DO NOT CONNECT
GND AVCC
C1 GND AVCC
C2 GND AVCC
GND
GND
GND
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AD6644
DEFINITIONS OF SPECIFICATIONS Analog Bandwidth Minimum Conversion Rate
The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.
Aperture Delay
The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels.
Noise (For Any Range Within the ADC)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance
VNOISE = | Z | x0.001 x 10
FSdBm - SignaldBFS 10
The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. The difference is then computed between both peak measurements.
Differential Nonlinearity
Where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value for the particular input level and Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc.
Signal-to-Noise Ratio (Without Harmonics)
The deviation of any code width from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing tENCH in text. At a given clock rate, these specs define an acceptable ENCODE duty cycle.
Full-Scale Input Power
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
Expressed in dBm. Computed using the following equation: V Full Scale rms | Z |Input = 10 log 0.001
2
The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or dBFS (always related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
PowerFull Scale

The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
Harmonic Distortion, 2nd
The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc.
Harmonic Distortion, 3rd
The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc.
Integral Nonlinearity
The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the 2nd and 3rd harmonic) reported in dBc.
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least-square curve fit.
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AD6644
EQUIVALENT CIRCUITS
VCH AVCC
DVCC
CURRENT MIRROR
BUF 500 T/H
AIN
VCL VCH AVCC 500 AIN BUF T/H BUF VREF
DVCC VREF D0-D13, OVR, DRY
VCL
Figure 2. Analog Input Stage
CURRENT MIRROR
Figure 5. Digital Output Stage
LOADS AVCC AVCC 10k ENCODE 10k 10k 10k ENCODE AVCC AVCC
AVCC AVCC 2.4V VREF
100 A
LOADS
Figure 3. ENCODE Inputs
Figure 6. 2.4 V Reference
AVCC
VREF AVCC AVCC
DVCC 10k
DMID
CURRENT MIRROR C1 OR C2
10k
Figure 4. Compensation Pin, C1 or C2
Figure 7. DMID Reference
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Typical Performance Characteristics- AD6644
0 -10 -20 -30 -40 ENCODE = 65MSPS AIN = 2.2MHz @ -1dBFS SNR = 74.5dB SFDR = 92dBc
75.0 ENCODE = 65MSPS, AIN = -1dBFS TEMP = -25 C, 25 C, 85 C T = -25 C 74.0
74.5
SNR - dB
-50 -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 15 20 FREQUENCY - MHz 25 30
T= 73.5
85 C
T=
25 C
73.0
72.5
72.0 0
5
10 15 20 FREQUENCY - MHz
25
30
Figure 8. Single Tone at 2.2 MHz
Figure 11. Noise vs. Analog Frequency (Nyquist)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 15 20 FREQUENCY - MHz 25 30 ENCODE = 65MSPS AIN = 15.5MHz @ -1dBFS SNR = 74dB SFDR = 90dBc
94 ENCODE = 65MSPS, AIN = -1dBFS
WORST-CASE HARMONIC - dBc
92 90 T= 88 86 84 82 80 0 25 C,
TEMP =
25 C,
25 C,
85 C
T= 85 C
25 C
5
10 15 20 25 ANALOG INPUT FREQUENCY - MHz
30
Figure 9. Single Tone at 15.5 MHz
Figure 12. Harmonics vs. Analog Frequency (Nyquist)
0 -10 -20 -30 -40
SNR - dB
75
ENCODE = 65MSPS AIN = 30MHz @ -1dBFS SNR = 73.5dB SFDR = 85dBc
LOW NOISE ANALOG SOURCE 74 73 72 71 70 69 68 0 PHASE NOISE OF ANALOG SOURCE DEGRADES PERFORMANCE
-50 -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 15 20 FREQUENCY - MHz 25 30
AIN = -1dBFS ENCODE = 65MSPS 10 20 30 40 50 60 70 80 ANALOG FREQUENCY - MHz 90 100
Figure 10. Single Tone at 30 MHz
Figure 13. Noise vs. Analog Frequency (IF)
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AD6644
100 95 90 WORST OTHER SPUR ENCODE = 65MSPS AIN = -1dBFS
0 -10 -20 -30 -40 -50 ENCODE = 65MSPS AIN = 15MHz, 15.5MHz @ -7dBFS NO DITHER
HARMONICS - dBc
85 80 75 70 HARMONICS (2nd, 3rd) 65 60 55 0 10 20 30 40 60 50 70 80 ANALOG FREQUENCY - MHz 90 100
-60 -70 -80 -90 -100 -110 -120 -130 0 5 10 15 20 FREQUENCY - MHz 25 30
Figure 14. Harmonics vs. Analog Frequency (IF)
Figure 17. Two Tones at 15 MHz and 15.5 MHz
120
WORST-CASE SPURIOUS - dBFS and dBc
110
WORST-CASE SPURIOUS - dBFS and dBc
110 100 90 80 70 60 50 40 30 20 10 0 -80 -70 -20 -10 -60 -50 -30 -40 ANALOG INPUT POWER LEVEL - dBFS 0 SFDR = 90dB REFERENCE LINE ENCODE = 65MSPS AIN = 15.5MHz dBc dBFS
dBFS 100 90 80 70 60 50 40 30 20 10 0 -77 -57 -47 -37 -67 -27 -17 INPUT POWER LEVEL - (F1 = F2) dBFS -7 SFDR = 90dB REFERENCE LINE ENCODE = 65MSPS F1 = 15MHz F2 = 15.5MHz
dBc
Figure 15. Single Tone SFDR
Figure 18. Two-Tone SFDR
0
100
SNR, WORST SPURIOUS - dB and dBc
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0
ENCODE = 65MSPS AIN = 19MHz, 19.5MHz @ -7dBFS NO DITHER
AIN = 2.2MHz @ -1dBFS 95 90 85 80 75 SNR 70 65 60 WORST SPUR
5
10
15 20 FREQUENCY - MHz
25
30
0
10
20
40 50 60 70 30 ENCODE FREQUENCY - MHz
80
90
Figure 16. Two Tones at 19 MHz and 19.5 MHz
Figure 19. SNR, Worst Spurious vs. Encode
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AD6644
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 15 20 FREQUENCY - MHz 25 30 ENCODE = 65MSPS AIN = 15.5MHz @ -29.5dBFS NO DITHER
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 15 20 FREQUENCY - MHz 25 30 ENCODE = 65MSPS AIN = 15.5MHz @ -29.5dBFS DITHER @ -19dBm
Figure 20. 1M FFT Without Dither
Figure 23. 1M FFT with Dither
100 90 ENCODE = 65MSPS AIN = 15.5MHz NO DITHER
100 90 ENCODE = 65MSPS AIN = 15.5MHz DITHER = -19dBm
WORST-CASE SPURIOUS - dBc
80 70 60 50 40 30 20 10 0 -90
WORST-CASE SPURIOUS - dBc
80 70 60 50 40 30 20 10
SFDR = 100dB REFERENCE LINE
SFDR = 90dB REFERENCE LINE
SFDR = 90dB REFERENCE LINE
-80
-20 -10 -70 -60 -50 -40 -30 ANALOG INPUT POWER LEVEL - dBFS
0
0 -90
-80
-60 -20 -70 -50 -40 -30 -10 ANALOG INPUT POWER LEVEL - dBFS
0
Figure 21. SFDR Without Dither
Figure 24. SFDR with Dither
95 2.2MHz
SNR, WORST SPURIOUS - dB and dBc
90
WORST SPUR ENCODE = 65MSPS
85 30.5MHz 80 2.2MHz 75 30.5MHz 70 SNR
65 -15.0
-10.0
5.0 -5.0 10.0 0 ENCODE INPUT POWER - dBm
15.0
Figure 22. SNR, Worst Spurious vs. Clamped Encode Power (See Figure 25)
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AD6644
THEORY OF OPERATION
0.1 F CLOCK SOURCE 100 ENCODE HSMS2812 DIODES
The AD6644 analog-to-digital converter (ADC) employs a three stage subrange architecture. This design approach achieves the required accuracy and speed while maintaining low power and small die size. As shown in the functional block diagram, the AD6644 has complementary analog input pins, AIN and AIN . Each analog input is centered at 2.4 V and should swing 0.55 V around this reference (Figure 2). Since AIN and AIN are 180 degrees out of phase, the differential analog input signal is 2.2 V peakto-peak. Both analog inputs are buffered prior to the first track-and-hold, TH1. The high state of the ENCODE pulse places TH1 in hold mode. The held value of TH1 is applied to the input of a 5-bit coarse ADC1. The digital output of ADC1 drives a 5-bit digitalto-analog converter, DAC1. DAC1 requires 14 bits of precision which is achieved through laser trimming. The output of DAC1 is subtracted from the delayed analog signal at the input of TH3 to generate a first residue signal. TH2 provides an analog pipeline delay to compensate for the digital delay of ADC1. The first residue signal is applied to a second conversion stage consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4. The second DAC requires 10 bits of precision which is met by the process with no trim. The input to TH5 is a second residue signal generated by subtracting the quantized output of DAC2 from the first residue signal held by TH4. TH5 drives a final 6-bit ADC3. The digital outputs from ADC1, ADC2, and ADC3 are added together and corrected in the digital error correction logic to generate the final output data. The result is a 14-bit parallel digital CMOS-compatible word, coded as two's complement.
APPLYING THE AD6644 Encoding the AD6644
T1-4T
ENCODE
AD6644
Figure 25. Crystal Clock Oscillator - Differential Encode
If a low jitter ECL/PECL clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown below. A device that offers excellent jitter performance is the MC100LVEL16 (or same family) from Motorola.
VT 0.1 F ENCODE ECL/ PECL 0.1 F ENCODE
AD6644
VT
Figure 26. Differential ECL for Encode
Analog Input
As with most new high-speed, high dynamic range analog-todigital converters, the analog input to the AD6644 is differential. Differential inputs allow much improvement in performance on-chip as signals are processed through the analog stages. Most of the improvement is a result of differential analog stages having high rejection of even order harmonics. There are also benefits at the PCB level. First, differential inputs have high commonmode rejection to stray signals such as ground and power noise. Also, they provide good rejection to common-mode signals such as local oscillator feedthrough. The AD6644 input voltage range is offset from ground by 2.4 V. Each analog input connects through a 500 resistor to a 2.4 V bias voltage and to the input of a differential buffer (Figure 2). The resistor network on the input properly biases the followers for maximum linearity and range. Therefore, the analog source driving the AD6644 should be ac-coupled to the input pins. Since the differential input impedance of the AD6644 is 1 k, the analog input power requirement is only -2 dBm, simplifying the driver amplifier in many cases. To take full advantage of this high-input impedance, a 20:1 transformer would be required. This is a large ratio and could result in unsatisfactory performance. In this case, a lower step-up ratio could be used. The recommended method for driving the analog input of the AD6644 is to use a 4:1 RF transformer. For example, if RT were set to 60.4 and RS were set to 25 , along with a 4:1 transformer, the input would match to a 50 source with a full-scale drive of 4.8 dBm. Series resistors (RS) on the secondary side of the transformer should be used to isolate the transformer from A/D. This will limit the amount of dynamic current from the A/D flowing back into the secondary of the transformer. The terminating resistor (RT) should be placed on the primary side of the transformer.
ANALOG INPUT SIGNAL T1-4T RT RS 0.1 F AIN RS AIN
The AD6644 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 70 MHz input signals when using a high-jitter clock source. See Analog Devices' Application Note AN-501, "Aperture Uncertainty and ADC System Performance" for complete details. For optimum performance, the AD6644 must be clocked differentially. The encode signal is usually ac-coupled into the ENCODE and ENCODE pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Shown below is one preferred method for clocking the AD6644. The clock source (low jitter) is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD6644 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD6644, and limits the noise presented to the ENCODE inputs. A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limiting resistor (typically 100 ) is placed in the series with the primary.
AD6644
Figure 27. Transformer-Coupled Analog Input Circuit
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REV. 0
AD6644
In applications where dc-coupling is required, a new differential output op amp from Analog Devices, the AD8138, can be used to drive the AD6644 (Figure 28). The AD8138 op amp provides single-ended-to-differential conversion, which reduces overall system cost and minimizes layout requirements.
CF
tion of high frequency, high resolution design practices. All of the digital outputs are segregated to two sides of the chip, with the inputs on the opposite side for isolation purposes. Care should be taken when routing the digital output traces. To prevent coupling through the digital outputs into the analog portion of the AD6644, minimal capacitive loading should be placed on these outputs. It is recommended that a fan-out of only one gate be used for all AD6644 digital outputs. The layout of the Encode circuit is equally critical. Any noise received on this circuitry will result in corruption in the digitization process and lower overall performance. The Encode clock must be isolated from the digital outputs and the analog inputs.
Jitter Considerations
499 5V VIN 499 VOCM 499 25 AIN DIGITAL OUTPUTS
AD8138
25
AD6644
AIN VREF
0.1 F
499 CF
Figure 28. DC-Coupled Analog Input Circuit
Power Supplies
The signal-to-noise ratio (SNR) for an ADC can be predicted. When normalized to ADC codes, Equation 1 accurately predicts the SNR based on three terms. These are jitter, average DNL error, and thermal noise. Each of these terms contributes to the noise within the converter.
2 2 V (1 + ) SNR = -20 x log N + (2 x x f ANALOG x t J RMS )2 + NOISE RMS 2 2N 1/ 2
Care should be taken when selecting a power source. Linear supplies are strongly recommended. Switching supplies tend to have radiated components that may be "received" by the AD6644. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 F chip capacitors. The AD6644 has separate digital and analog power supply pins. The analog supplies are denoted AVCC and the digital supply pins are denoted DVCC. AVCC and DVCC should be separate power supplies. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that AVCC must be held within 5% of 5 V. The AD6644 is specified for DVCC = 3.3 V as this is a common supply for digital ASICs.
Output Loading
(1)
fANALOG tJ RMS N
= analog input frequency. = rms jitter of the encode (rms sum of encode source and internal encode circuitry). = average DNL of the ADC (typically 0.41 LSB). = Number of bits in the ADC.
VNOISE RMS = V rms thermal noise referred to the analog input of the ADC (typically 2.5 LSB). For a 14-bit analog-to-digital converter like the AD6644, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. The chart below shows a family of curves that demonstrates the expected SNR performance of the AD6644 as jitter increases. The chart is derived from the above equation. For a complete discussion of aperture jitter, please consult Analog Devices' Application Note AN-501, "Aperture Uncertainty and ADC System Performance."
80 AIN = 30MHz 75 AIN = 70MHz
Care must be taken when designing the data receivers for the AD6644. It is recommended that the digital outputs drive a series resistor (e.g. 100 ) followed by a gate like 74LCX574. To minimize capacitive loading, there should only be one gate on each output pin. An example of this is shown in the evaluation board schematic shown in Figure 30. The digital outputs of the AD6644 have a constant output slew rate of 1 V/ns. A typical CMOS gate combined with a PCB trace will have a load of approximately 10 pF. Therefore, as each bit switches, 10 mA (10 pF 1 V 1 ns) of dynamic current per bit will flow in or out of the device. A full scale transition can cause up to 140 mA (14 bits 10 mA/bit) of current to flow through the output stages. The series resistors should be placed as close to the AD6644 as possible to limit the amount of current that can flow into the output stage. These switching currents are confined between ground and the DVCC pin. Standard TTL gates should be avoided since they can appreciably add to the dynamic switching currents of the AD6644. It should also be noted that extra capacitive loading will increase output timing and invalidate timing specifications. Digital output timing is guaranteed with 10 pF loads.
Layout Information
SNR - dB
70 AIN = 110MHz 65
AIN = 150MHz 60 AIN = 190MHz 55 0
0.1
0.2
0.3 0.4 JITTER - ps
0.5
0.6
The schematic of the evaluation board (Figure 30) represents a typical implementation of the AD6644. A multilayer board is recommended to achieve the best results. It is highly recommended that high-quality, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. The pinout of the AD6644 facilitates ease of use in the implementaREV. 0 -13-
Figure 29. SNR vs. Jitter
AD6644
EVALUATION BOARD
The evaluation board for the AD6644 is straightforward, containing all required circuitry for evaluating the device. The only external connections required are power supplies, clock, and the analog inputs. The evaluation board includes the option for an onboard clock oscillator for ENCODE. Power to the analog supply pins of the AD6644 is connected via the power terminal block (PCTB2). Power for the digital interface is supplied via pin 1 of J6. The J2 connector mates directly with SoftCell Receive Signal Processor (AD6620, AD6624) evaluation boards, allowing complete evaluation of system performance. The analog input is connected via a BNC connector AIN, which is transformer-coupled to the AD6644 inputs. The transformer has a turns ratio of 1:4 to reduce the amount of input power required to drive the AD6644.
The Encode signal may be generated using an onboard crystal oscillator, U5. The on-board oscillator may be replaced by an external encode source via the SMA connector labeled OPT_CLK or BNC connector labeled ENCODE. If an external source is used, it must be a high-quality and very low-phase noise source. The AD6644 output data is latched using 74LCX574 (U7, U2) latches. The clock for these latches is determined by selecting jumper E3-E4 or E4-E5. E3 to E5 is a just a gate delayed version of the clock, while connecting E4 to E5 utilizes the Data Ready of the AD6644 to latch the output data. A clock is also distributed with the output data (J2) that is labeled BUFLAT (Pin 19 and 20, J2).
AD6644ST/PCB Bill of Material
Item 1 2
Quantity 2 19
Reference C1, C2 C3, C7, C8, C9, C10, C11, C16, C30, C31, C32, C4, C22, C23, C24, C25, C26, C27, C28, C29 C12, C13, C14, C17, C18, C19, C20, C21 CR1 E3, E4, E5 F1, F2, F3, F4 J1, J6 J2 J3 J4, J5 R1 R2 R3, R4, R5, R8 R6, R7 R9 R10 R35 R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65 T2, T3 U1 U2, U7 U3 U4, U6 U5
Description Tantalum Chip Capacitor 10 F Ceramic Chip Capacitor 0508, 0.1 F Ceramic Chip Capacitor 0508, 0.01 F HSMS2812 Surface Mount Diode 3-Pin Header Ferrite (Optional) PCTB2 50-Pin Double Row Header SMA Connector BNC Connector Surface-Mount Resistor 1206, 100 Surface-Mount Resistor 1206, 60.4 Surface-Mount Resistor 0805, 499 (Optional, DC-Coupling Only) Surface-Mount Resistor 0805, 25 Surface-Mount Resistor 0805, 348 Surface-Mount Resistor 0805, 615 Surface-Mount Resistor 0805, 49.9 Surface-Mount Resistor 0402, 100
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
8 1 1 4 2 1 1 2 1 1 4 2 1 1 1 30
19 20 21 22 23 24
2 1 2 1 2 1
Surface-Mount Transformer Mini-Circuits T4-1, 1:4 Ratio AD6644AST 14-Bit 65 MSPS A/D Converter 74LCX574 Octal Latch AD8138 Single-to-Differential Amplifier (Optional - DC Coupling Only) NC7SZ32 Two Input OR Gate CTS Reeves Full-Size MX045 Crystal Clock Oscillator
-14-
REV. 0
SMA
DR_OUT
3P3V GND
D13
DRY
D12 D11 D10 D9 D8
GND D5
2 3 3 37 36 35 GND VREF GND ENC ENC GND GND AVCC OVR 31 30 DNC AVCC GND AVCC GND AVCC GND AIN AIN GND DVCC 32 DMID D1 D0 D2
R1 100
38
2
3P3V 1 GND 2
DVCC 5 6 7 8 9 10 D3 39 4
D7 D6 DVCC
1
4
T1-4T 3
D4
BNC
AVCC
GND
AVCC
GND
AVCC
GND C1
GND AVCC
GND C2 GND
2 1 V- 4
AD8138
5VA GND 5VA GND 5VA GND GND 5VA GND
6 2
V
5
R6 25
AVCC
BNC
R8 499 GND R4 499 T3
6 1:4 2 3 T1-4T 5 4 1
GND 5VA
REV. 0
J6
2 1 1 2 3 4 5 6 7 8 9 10 D0 D1 1 3 5 7 9 11 13 15 17 19 V GND 3 4 21 2 23 25 27 29 20 19 31 33 35 37 39 41 43 45 47 49 OUT_EN VCC 19 20 1 2
GND
F2 FERRITE 3P3V
U7
PCTB2
1
U5
NC
VCC
14
F3 FERRITE J2
1
2
5VA
C22 100nF
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
7
GND OUT
8
K1115
3P3V
3P3VD
OPT_CLK J3
V 4
R10 615 OPT_LAT E3 E4 E5 BUFLAT
1
R45 R46 R47 R48 R49 R50 R51 R44
Q0 18 Q1 17 D2 Q2 16 D3 Q3 15 D4 Q4 14 D5 Q5 13 D6 Q6 12 D7 Q7 11 GND CLOCK
C3 100nF 74LCX574 3P3VD U6 5 BUFLAT NC7SZ32 DR_OUT
1
U4 5
GND 100 100 100 100 100 100 100 100 GND B13 B12 B11 B10 B09 B08 B07 B06
3P3VD R65 100 100 R52 R53 100 R54 100 100 R55 100 R56 100 R57 R64 100 BUFLAT
2
R9 348 NC7SZ32 VREF C32 100NF
1 2 3 D0 D1
GND 3
U2
OUT_EN VCC
ENC J4 U1 HSMS2812
C4 100nF
52 51 50 49 48 47 46 45 44 43 42 41 40
R35 49.9 CR1
1 5 6 7 8 9 10 11 12 13 2
6
1
C28 100nF GND 4 ENC ENC
T2
1:4
R43 R42 R41 R40 R39 R38 R36
3P3VD R63 R62 R61 R60 R59 R58 R37
Q0 18 Q1 17 D2 Q2 16 Q3 D3 15 D4 Q4 14 D5 Q5 13 D6 Q6 12 D7 Q7 11 GND CLOCK
100 100 100 100 100 100 100 BUFLAT 74LCX574
C29 100nF
PREF 34 GND 33 3P3V
GND 100 100 100 100 100 100 100 GND GND
B05 B04 B03 B02 B01 B00 GND GND GND GND GND GND OVR GND
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND HEADR50
Figure 30. AD6644ST/PCB Schematic (GS02357D Schematic)
AD6644ST
R5 499 5VA
8 3
-15-
U3 R7 25
14 15 16 17 18 19 20 21 22 23 24 25 26
C27 100nF 5VA 29 GND 28 5VA 27 GND
AIN J5
GND 5VA 5VA GND AIN AIN GND
1
R3 499
H4 H3 H2
R2 60.4 VREF
C8 100nF
C7 100nF
H1 MOUNTING HOLES
J1
2 1
GND
F1 FERRITE
1 2
C30 100nF
5VA PCTB2 C2 10 F C16 100nF C17 10nF C18 10nF C19 10nF C20 10nF F4 FERRITE 3P3V C1 10 F C9 100nF C10 100nF C11 100nF C12 10nF C13 10nF
1 2
C21 10nF
3P3VD C14 10nF C23 100nF C24 100nF C25 100nF C26 100nF
AD6644
NOTE: THE DOTTED LINE REPRESENTS AN OPTIONAL ANALOG DRIVE INPUT
AD6644
Figure 31. AD6644ST/PCB Top Side Silkscreen
Figure 32. AD6644ST/PCB Top Side Copper
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REV. 0
AD6644
Figure 33. AD6644ST/PCB Bottom Side Silkscreen
Figure 34. AD6644ST/PCB Bottom Side Copper
REV. 0
-17-
AD6644
Figure 35. AD6644ST/PCB Ground Layer - Layers 2 and 5 (Negative)
Figure 36. AD6644ST/PCB "Split" Power Layer - Layers 3 and 4 (Negative)
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REV. 0
AD6644
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
52-Terminal Plastic Low Profile Quad Flatpack (ST-52)
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45)
40 39
0.472 (12.00) SQ
27 26
SEATING PLANE TOP VIEW
(PINS DOWN)
0.394 (10.0) SQ
52
14 1 13
0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35)
0.026 (0.65) BSC
0.015 (0.38) 0.009 (0.22)
REV. 0
-19-
PRINTED IN U.S.A.
C3812-5-4/00 (rev. 0)

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